A router apparatus is known that enables data communication between computers or the like via the Internet or an intranet, for example, by connecting a local area network (“LAN”) and a wide area network (“WAN”) in a client/server model, for example. FIG. 1 depicts a block diagram of a router apparatus 100 according to the related art. A packet is received at a reception port 10 and then supplied to a packet buffer 12, a write control unit 14, and an FCS (frame check sequence) checking unit 16. The write control unit 14 writes the received packet in the packet buffer 12 while supplying a write control signal including a write address to the packet buffer 12. The FCS checking unit 16 performs an FCS check on the received packet to check for errors in the received packet. If there is an error, the packet is discarded; if there is no error, the number of packets accumulated in the packet buffer 12 that is monitored by a volume monitoring unit 18 is incremented.
In the packet buffer 12, SOP (Start Of Packet) and EOP (End Of Packet) indicators indicating the start and the end, respectively, of the packet are also written as parallel information in the packet buffer 12, together with packet data. The parallel information is also read when the packet data is read.
The volume monitoring unit 18 reads the number of accumulated packets in the packet buffer 12 and notifies a control unit 20. If the number of accumulated packets is plus (greater than zero), the read control unit 20 reads a packet from the packet buffer 12 while supplying a read control signal, including a read address, to the packet buffer 12. The packet read from the packet buffer 12 together with the parallel information SOP and EOP is supplied to an EOP extracting unit 22, a DA (destination address) extracting unit 24, and a phase adjusting unit 28. Upon extraction of the EOP indicator indicating the end of the packet, the EOP extracting unit 22 notifies the read control unit 20.
The DA extracting unit 24 extracts the DA of the packet read from the packet buffer 12 and supplies the DA to a route search unit 26. The route search unit 26 searches its own internal route search table with reference to the DA, and supplies obtained route information to a switch 30. A phase adjusting unit 28 performs phase adjustment by delaying the packet by a time required for route search before supplying the packet to the switch 30. The switch 30 selects one of transmit ports 32a through 32d in accordance with the route information, and then outputs the packet via the selected transmit port.
Japanese Laid-Open Patent Application No. 2000-244570 discloses that a received packet is stored in a packet buffer by a forwarding engine, and header information is stored in a header RAM. A search engine searches the header information for forwarding control information and writes the forwarding control information in the header RAM. Based on the information from the packet buffer and the header RAM, an output packet is generated by the forwarding engine and outputted to a forwarding destination.
In the method discussed with reference to FIG. 1, the packet is first written in the packet buffer 12 and then the destination information DA is read from the packet buffer 12 in order to obtain route information using the route search unit 26. As a result, delivery of the packet is delayed by the time required for the route search that is conducted after the packet is read from the packet buffer 12.